CPC H04W 56/0035 (2013.01) [H04W 56/001 (2013.01); H04W 56/004 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code;
wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:
estimate a change in a propagation delay at two time instants;
measure a time period of the two time instants using a local clock of a network node, wherein the two time instants correspond to a known timing of a received signal;
subtract the change in the propagation delay from a measured time period Δt;
calculate a difference between a subtracted time period and the known timing of the received signal; and
convert the difference to a frequency offset value Δf to synchronize downlink transmission frequency between the network node and a parent node.
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