CPC H04W 52/0232 (2013.01) [H04W 74/04 (2013.01); H04W 74/0841 (2013.01)] | 17 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one non-transitory memory storing instructions executed by the at least one processor to cause the apparatus at least to:
determine a time period for monitoring a random access response;
identify that a wake-up signal occasion for a wakeup signal is overlapping a predetermined time period for the random access response, wherein the predetermined time period comprises the determined time period; and
based on the identifying, control monitoring of the wake-up signal occasion for a wake-up signal;
based on the controlling, not monitor the wake-up signal occasion during the predetermined time period for the random access response;
determine that the random access response has been triggered; and
based on the determining, cause the apparatus to not monitor the wake-up signal occasion during the predetermined time period for the random access response; and
start a discontinuous reception timer at a next discontinuous reception OnDuration occasion.
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