	US 11,996,937 B2
	Encoding device, encoding method, decoding device, decoding method, and program
Tatsuya Sugioka, Tokyo (JP); Toshihisa Hyakudai, San Diego, CA (US); Masayuki Unuma, Kanagawa (JP); Daisuke Okazawa, Kanagawa (JP); Aritoshi Kimura, Kanagawa (JP); and Hiroshi Shiroshita, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/636,989
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jun. 30, 2020, PCT No. PCT/JP2020/025630 § 371(c)(1), (2) Date Feb. 21, 2022, PCT Pub. No. WO2021/039098, PCT Pub. Date Mar. 4, 2021.
Claims priority of application No. 2019-157636 (JP), filed on Aug. 30, 2019.
Prior Publication US 2023/0308210 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 1/00 (2006.01); H03M 5/14 (2006.01); H03M 13/15 (2006.01); H04L 25/49 (2006.01)

CPC H04L 1/0057 (2013.01) [H03M 5/145 (2013.01); H03M 13/1515 (2013.01); H04L 1/0045 (2013.01); H04L 25/49 (2013.01)]

19 Claims

1. An encoding device comprising:

a memory storing program code, and

a processor configured to execute the program code to perform operations comprising:

dividing input data into data strings of N bits, the data strings including a first data string;

calculating a running disparity for the data strings;

determining whether the first data string is to be inverted based upon the calculated running disparity;

setting a flag for the first data string to a first value when it is determined that the first data string is not to be inverted, and setting the flag for the first data string to a second value and inverting the first data string when it is determined that the first data string is to be inverted; and

outputting the first data string.