| CPC H04J 11/0073 (2013.01) [H04J 13/0025 (2013.01); H04L 27/2607 (2013.01); H04L 27/2613 (2013.01); H04L 27/2614 (2013.01); H04L 27/2692 (2013.01); H04L 27/26136 (2021.01); H04L 27/2636 (2013.01)] | 13 Claims |
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1. A base station operable to encode a primary synchronization signal for transmission to a user equipment (UE), the base station comprising:
one or more processors configured to:
identify, at the base station, a sequence d(n) for a primary synchronization signal, wherein:
the sequence d(n) is defined by: d(n)=1−2s(n);
s(n) is a maximum run length sequence (m-sequence); and
s(n) is provided as s(n+7)=(s(n+4)+s(n)) mod 2, where 0≤n≤127;
generate, at the base station, the primary synchronization signal based on the sequence d(n), wherein to generate the primary synchronization signal comprises:
modulate the sequence d(n) to form a modulated sequence;
multiply the modulated sequence with an alternating sequence of {+1, +j};
perform a discrete Fourier transform (DFT) operation to map the modulated sequence to subcarriers in a frequency domain; and
perform an inverse DFT operation to the modulated sequence to obtain synchronization signal (SS) orthogonal frequency division multiplexing (OFDM) symbols in a time domain;
encode, at the base station, the primary synchronization signal for transmission to the UE; and
a memory interface configured to retrieve from a memory the primary synchronization signal.
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