US 11,996,860 B2
Scaled bit flip thresholds across columns for irregular low density parity check decoding
Eyal En Gad, Santa Clara, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); and Yoav Weinberg, Toronto (CA)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 1, 2022, as Appl. No. 17/829,924.
Prior Publication US 2023/0396269 A1, Dec. 7, 2023
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1108 (2013.01) [H03M 13/1128 (2013.01); H03M 13/1148 (2013.01); H03M 13/6511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
reading a sense word from the memory device;
executing a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results;
determining a syndrome for the sense word using the plurality of parity check equation results;
determining whether the syndrome for the sense word satisfies a codeword criterion; and
responsive to the syndrome for the sense word not satisfying the codeword criterion, determining a scaled bit flip threshold and performing an iterative low density parity check (LDPC) correction process using the scaled bit flip threshold to correct one or more errors in the sense word, wherein the scaled bit flip threshold is based on a relationship between a respective number of parity check equation results that are in an unsatisfied state and a respective total number of parity check equations associated with each bit of the sense word from a previous iteration of the iterative LDPC correction process.