| CPC H03L 7/091 (2013.01) [H03L 7/0891 (2013.01); H03L 7/099 (2013.01)] | 20 Claims |
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1. A sub-sampling phase lock loop comprising:
a plurality of samplers configured to:
receive a plurality of clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator,
receive a plurality of reference signal phases of a reference signal generated by a reference clock generator, and
obtain a plurality of sampled values by sampling the plurality of clock signal phases generated by the voltage controlled oscillator at sampling edges of the plurality of reference signal phases over a reference clock cycle of the reference signal;
a phase detector configured to:
select a phase for a particular instant kTref of the reference signal based on at least one sampled value satisfying a predetermined criteria, said phase corresponding to a clock signal phase value and a reference signal phase value respectively selected out of the plurality of clock signal phases and the plurality of reference signal phases, where “k” refers to a numbering of the particular instant,
track the selected phase at every successive instant (k+1)Tref of the reference signal, and
determine sampled values associated with the selected phase in the every successive instant (k+1)Tref of the reference signal at every instant of the reference clock cycle; and
a processing unit configured to:
acquire frequency information at the every successive instant (k+1)Tref based on the tracking of the selected phase,
wherein the acquired frequency information comprises:
a frequency offset value determined based on a differential between the sampled values within a successor instant (k+1)Tref of the reference signal and the sampled values in the particular instant kTref of the reference signal, and
a direction traversed by the selected phase between the particular instant kTref and successor instant (k+1)Tref.
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