US 11,996,848 B1
Compensation for clock frequency modulation
Aaron D. Willey, Santa Clara, CA (US); and Karthik Gopalakrishnan, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,622.
Int. Cl. H03K 5/135 (2006.01); H03K 5/14 (2014.01); H03K 7/06 (2006.01)
CPC H03K 5/135 (2013.01) [H03K 5/14 (2013.01); H03K 7/06 (2013.01)] 20 Claims
OG exemplary drawing
 
6. A system comprising:
a reference clock circuit configured to produce a clock signal;
a frequency modulation circuit coupled to the reference clock circuit and configured to modulate a frequency of the clock signal;
a phase compensation circuit coupled to the reference clock circuit and configured to compensate for a phase error produced by modulating the frequency of the clock signal; and
a latch circuit coupled to the reference clock circuit and triggered by the modulated and phase compensated clock signal.