| CPC H03K 3/0372 (2013.01) [H03K 3/012 (2013.01); H03K 3/3562 (2013.01); H03K 19/20 (2013.01)] | 7 Claims |
|
1. A flip-flop circuit comprising:
a first latch circuit connected between a first node and a second node; and
a second latch circuit connected between the second node and a third node,
wherein the first latch circuit comprises:
a first p-type transistor, a second p-type transistor, and a first n-type transistor connected in series between a power supply terminal and a power ground terminal, which the first node is a common drain end of the second p-type transistor and the first n-type transistor; and
a NOR circuit configured to receive a signal of the first node and an inverted clock signal, perform a NOR operation, and output an operation result to the second node, and
wherein the NOR circuit includes a third p-type transistor and a fourth p-type transistor connected in series between the power supply terminal and the second node, which a common end between the third p-type transistor and the fourth p-type transistor is connected to a gate of the first p-type transistor.
|