| CPC H03K 19/0013 (2013.01) [G01R 31/318536 (2013.01)] | 20 Claims |
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1. An integrated circuit, comprising:
a flip-flop circuit, arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and
a gating circuit, coupled to the flip-flop circuit, the gating circuit being arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal, wherein during a time interval between two consecutive signal transitions of the input clock signal, a signal transition of one of the first clock signal and the second clock signals occurs, and the other of the first clock signal and the second clock signals stays at a same logic level determined according to a signal level of the master signal;
wherein a number of signal transitions of the first clock signal during a period of time and a number of signal transitions of the second clock signal during the period of time are not greater than a number of signal transitions of the input clock signal during the period of time during the writing mode and the storing mode.
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