US 11,996,807 B2
Low noise trans-impedance amplifier
Haiyan Zhou, Pudong New District (CN); Ronghui Kong, Pudong New District (CN); and Jiazhou Liu, Pudong (CN)
Assigned to Beken Corporation, Shanghai (CN)
Filed by Beken Corporation, Pudong New District (CN)
Filed on May 5, 2022, as Appl. No. 17/662,194.
Claims priority of application No. 202210352454.X (CN), filed on Apr. 4, 2022.
Prior Publication US 2023/0318535 A1, Oct. 5, 2023
Int. Cl. H03F 1/08 (2006.01); H03F 1/26 (2006.01); H03F 3/45 (2006.01); H04B 10/60 (2013.01)
CPC H03F 1/083 (2013.01) [H03F 1/26 (2013.01); H03F 3/45 (2013.01); H04B 10/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A trans-impedance amplifier (TIA) (200) comprising:
an input stage (IS) comprising:
a first and a second input PMOS transistors (PM1, PM2);
a first and a second load NMOS transistors (NM1, NM2), wherein drains of the first and the second input PMOS transistors and drains of the first and the second load NMOS transistors are electrically connected; and
a first and a second differential voltage input nodes (Vinp, Vinn) respectively electrically connected to gates of the first and the second input PMOS transistors; and
an output driving stage (ODS) comprising a first and a second output circuits (OC1, OC2), each of the first and the second output circuits comprising:
a first pair of PMOS and NMOS transistors (MP3, MN3) electrically connected in parallel;
a second pair of PMOS and NMOS transistors (MP5, MNp) electrically connected in series;
a pair of capacitors (C1, C3) electrically connected in series; and
a differential output node (Voutp) electrically connected to a drain of a NMOS transistor (NMp) of the second pair of PMOS and NMOS transistors.