US 11,996,447 B2
Field effect transistors with gate electrode self-aligned to semiconductor fin
Sean T. Ma, Portland, OR (US); Matthew V. Metz, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Gilbert Dewey, Hillsboro, OR (US); Chandra S. Mohapatra, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); Anand S. Murthy, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,859.
Application 17/677,859 is a division of application No. 16/303,654, granted, now 11,276,755, previously published as PCT/US2016/038208, filed on Jun. 17, 2016.
Prior Publication US 2022/0181442 A1, Jun. 9, 2022
Int. Cl. H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/8258 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/1054 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02546 (2013.01); H01L 21/02639 (2013.01); H01L 21/8258 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method of forming a field effect transistor (FET) structure, the method comprising:
receiving a workpiece including a sub-fin surrounded by isolation dielectric, wherein the sub-fin comprises a first semiconductor material having a first bandgap;
forming a fin wider than the sub-fin by epitaxially growing a second semiconductor material from a portion of the first semiconductor material not covered by the isolation dielectric, wherein the second semiconductor material has a higher carrier mobility than that of silicon and a bandgap narrower than that of the first semiconductor material,
forming source and drain semiconductor material at opposite ends of the fin, and laterally overhanging the isolation dielectric;
forming a gate insulator over a channel region of the fin; and
forming a gate electrode over the gate insulator, wherein a portion of the gate electrode adjacent to a sidewall of the fin is above the isolation dielectric.