US 11,996,439 B2
Integrated circuit including trench capacitor
Wen-Feng Kuo, Hsinchu (TW); Chung-Chuan Tseng, Hsinchu (TW); and Chia-Ping Lai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 9, 2022, as Appl. No. 17/740,271.
Application 17/740,271 is a division of application No. 16/518,257, filed on Jul. 22, 2019, granted, now 11,329,125, issued on May 10, 2022.
Claims priority of provisional application 62/734,644, filed on Sep. 21, 2018.
Prior Publication US 2022/0271119 A1, Aug. 25, 2022
Int. Cl. H01L 23/64 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/91 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a capacitor comprising:
etching a plurality of primary trenches into a first region of a substrate, each of the primary trenches extending in a first direction;
etching a plurality of secondary trenches into the first region of the substrate, each of the secondary trenches extending in a second direction other than the first direction,
wherein adjacent secondary trenches of the plurality of secondary trenches and adjacent primary trenches of the plurality of primary trenches jointly define an island;
etching the island to recess an upper surface of the island relative to an upper surface of a second region of the substrate,
wherein the second region of the substrate surrounds the first region of the substrate;
depositing a first dielectric layer into each of the primary trenches, into each of the secondary trenches, and on the island; and
depositing a first conductive layer on the first dielectric layer.