US 11,996,411 B2
Stacked forksheet transistors
Cheng-Ying Huang, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); Anh Phan, Beaverton, OR (US); Nicole K. Thomas, Portland, OR (US); Urusa Alaan, Hillsboro, OR (US); Seung Hoon Sung, Portland, OR (US); Christopher M. Neumann, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Patrick Morrow, Portland, OR (US); Hui Jae Yoo, Portland, OR (US); Richard E. Schenker, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); and Ehren Mannebach, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/913,796.
Prior Publication US 2021/0407999 A1, Dec. 30, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H10B 12/00 (2023.01)
CPC H01L 27/0924 (2013.01) [H01L 29/0673 (2013.01); H01L 29/4232 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01); H10B 12/056 (2023.02)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a backbone;
a first transistor device comprising a first vertical stack of semiconductor channels adjacent to an edge of the backbone; and
a second transistor device comprising a second vertical stack of semiconductor channels adjacent to the edge of the backbone, the second transistor device stacked on the first transistor device.