US 11,996,404 B2
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
Cheng-Ying Huang, Hillsboro, OR (US); Gilbert Dewey, Hillsboro, OR (US); Ashish Agrawal, Hillsboro, OR (US); Kimin Jun, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Zachary Geiger, Hillsboro, OR (US); Cory Bomberger, Portland, OR (US); Ryan Keech, Portland, OR (US); Koustav Ganguly, Hillsboro, OR (US); Anand Murthy, Portland, OR (US); and Jack Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 1, 2021, as Appl. No. 17/540,120.
Application 17/540,120 is a continuation of application No. 16/728,983, filed on Dec. 27, 2019, granted, now 11,244,943.
Prior Publication US 2022/0093586 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/06 (2006.01); H01L 21/683 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 21/6835 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 2221/68363 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a level of metallization over a first transistor structure; and
a second transistor structure over the level of metallization, the second transistor structure comprising:
a gate electrode coupled with an interconnect feature of the level of metallization, wherein the gate electrode comprises a work function metal layer in contact with a gate insulator, and a second metal layer in contact with the work function metal layer, and wherein a layer comprising silicon is in contact with the second metal layer;
a channel material layer over the gate electrode, and the gate insulator therebetween, wherein the channel material layer comprises a monocrystalline semiconductor; and
a source material and a drain material coupled to the channel material layer.
 
13. An integrated circuit (IC) structure, comprising:
a level of metallization over a first transistor structure; and
a plurality of NMOS transistor structures over the level of metallization, the NMOS transistor structures comprising:
a plurality of co-planar gate electrodes, each coupled with an interconnect feature of the level of metallization;
a plurality of co-planar regions of channel material over corresponding ones of the gate electrodes, and a gate insulator between the gate electrodes and the regions of channel material, wherein the channel material comprises a monocrystalline semiconductor; and
a plurality of source and drain materials coupled to corresponding ones of the regions of channel material.