US 11,996,370 B2
Manufacturing method of a semiconductor memory device
Kun Young Lee, Seoul (KR); and Tae Kyung Kim, Cheongju-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 20, 2023, as Appl. No. 18/303,975.
Application 17/715,750 is a division of application No. 16/663,119, filed on Oct. 24, 2019, granted, now 11,309,256, issued on Apr. 19, 2022.
Application 18/303,975 is a continuation of application No. 17/715,750, filed on Apr. 7, 2022, granted, now 11,705,402.
Claims priority of application No. 10-2019-0051780 (KR), filed on May 2, 2019.
Prior Publication US 2023/0260928 A1, Aug. 17, 2023
Int. Cl. H01L 21/66 (2006.01); H01L 23/544 (2006.01); H01L 25/00 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 22/14 (2013.01); H01L 25/50 (2013.01); H01L 28/60 (2013.01); H01L 2223/54426 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
processing a first substrate, wherein processing the first substrate comprises:
embedding a sacrificial material in the first substrate;
disposing a first align mark over the sacrificial material; and
disposing a first structure over a first surface of the first substrate;
exposing the sacrificial material by removing a part of the first substrate from a rear surface of the first substrate opposite the first surface of the first substrate;
removing the sacrificial material;
processing a second substrate, wherein processing the second substrate comprises disposing a second align mark and a second structure at a surface of the second substrate;
disposing the first substrate over the second substrate such that the second structure and the first structure face each other; and
coupling the first structure and the second structure by checking alignment of the first align mark with the second align mark through a region from which the sacrificial material was removed.