US 11,996,362 B2
Integrated circuit device with crenellated metal trace layout
Patrick Morrow, Portland, OR (US); Mauro J. Kobrinsky, Portland, OR (US); Mark T. Bohr, Aloha, OR (US); Tahir Ghani, Portland, OR (US); Rishabh Mehandru, Portland, OR (US); and Ranjith Kumar, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/493,715.
Application 17/493,715 is a continuation of application No. 16/348,105, granted, now 11,139,241, previously published as PCT/US2016/065423, filed on Dec. 7, 2016.
Prior Publication US 2022/0028779 A1, Jan. 27, 2022
Int. Cl. H01L 23/528 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/772 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/528 (2013.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 21/30604 (2013.01); H01L 21/768 (2013.01); H01L 21/76898 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/522 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/4175 (2013.01); H01L 29/41791 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/772 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) cell structure, comprising:
a plurality of first traces that have a first trace width and extend in a first direction over a front side of a plurality of transistors, wherein individual ones of the first traces are coupled to a drain region of at least one of the transistors;
a back-side interconnect trace under a back side of the transistors, and coupled to a source region of at least one of the transistors;
a set of three adjacent second traces that extend a same length in a second direction, orthogonal to the first direction, wherein an outer pair of second traces have first and second opposite ends that are both substantially aligned in the first direction, and wherein a center one of the second traces has first and second opposite ends that are both laterally staggered from the opposite ends of the outer pair of second traces in the first direction by approximately the first trace width summed with half a distance between immediately adjacent ones of the first traces and
a plurality of gate electrode traces under the first and second traces, and extending in the second direction, wherein one of the gate electrode traces is between the center one of the second traces and each of the outer pair of the second traces.