US 11,996,352 B2
Semiconductor devices including supporter
Woosung Yang, Gwangmyeong-si (KR); Jiyoung Kim, Hwaseong-si (KR); and Jiwon Kim, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 16, 2022, as Appl. No. 17/888,727.
Application 17/888,727 is a continuation of application No. 16/989,017, filed on Aug. 10, 2020, granted, now 11,437,300.
Claims priority of application No. 10-2020-0007187 (KR), filed on Jan. 20, 2020.
Prior Publication US 2022/0392829 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H01L 23/481 (2013.01) [H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate including a first region, a second region, and a third region;
a horizontal conductive layer on the substrate;
a supporter on the horizontal conductive layer, the supporter including a first portion in the first region and a second portion in the second region, and a third portion in the third region;
a connection conductive layer between the first portion of the supporter and the horizontal conductive layer;
a connection mold layer between the third portion of the supporter and the horizontal conductive layer; and
a cell channel structure in the first region to pass through a stacked structure where a plurality of insulation layers and a plurality of wiring layers are alternately stacked and the supporter and extend to an inner portion of the horizontal conductive layer;
wherein a level of an upper surface of the supporter in the second region is lower than a level of an upper surface of the supporter in the third region.