| CPC H01L 22/12 (2013.01) [G03F 7/70525 (2013.01); G03F 7/7065 (2013.01); H01L 21/76838 (2013.01); H01L 23/5226 (2013.01)] | 7 Claims |
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1. A manufacturing method of a semiconductor device, the manufacturing method comprising:
inspecting each of plural chip regions of a substrate and determining the inspected chip region as a non-defective chip region or a defective chip region, the substrate including the plural chip regions formed as one system, and the plural chip regions being arranged in a planar direction on the substrate; and
forming a wiring, the wiring being connected to an electrode of the non-defective chip region among the plural chip regions, and the wiring being not connected to an electrode of the defective chip region among the plural chip regions,
wherein:
the forming of the wiring includes:
forming plural via openings on the electrodes of the plural chip regions; and
forming a line above the via opening, the line being connected to the electrode through the via opening of the non-defective chip region, and the line extending to bypass the via opening of the defective chip region, and
the forming of the line includes:
forming a resist covering the plural via openings;
forming a first latent image pattern on the resist by subjecting the non-defective chip region to exposure with a first mask, the first latent image pattern passing through an upper side of the via opening;
forming a second latent image pattern on the resist by subjecting the defective chip region to exposure with a second mask, the second latent image pattern bypassing an upper side of the via opening;
developing the first latent image pattern and the second latent image pattern to form a first groove pattern and a second groove pattern on the resist; and
embedding an electrically conductive substance in the first groove pattern and the second groove pattern to form the line.
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