CPC G11C 8/12 (2013.01) [G06F 9/3804 (2013.01); G06F 12/0246 (2013.01); G11C 11/4074 (2013.01); G06F 2212/1028 (2013.01)] | 20 Claims |
1. A method for processing computer instructions, the method comprising:
receiving, by an instruction dispatch unit of a processor, an instruction that specifies a core instruction state for the instruction, wherein the instruction references low latency data;
storing, by the instruction dispatch unit, the core instruction state into a first selectably-powered portion of an instruction state memory configured to store core instruction state and not low-latency data; and
storing, by the instruction dispatch unit, the low latency data into a row that is already powered on and that includes at least one entry having a type that matches the low latency data, the row being of a second selectably-powered portion of the instruction state memory configured to store low latency data and not core instruction state for instructions.
|