US 11,996,165 B2
Memory chip and operating method thereof
Hsiang-Chi Cheng, Hsin-Chu (TW); Shyh-Bin Kuo, Hsin-Chu (TW); Yi-Cheng Lai, Hsin-Chu (TW); Chung-Hung Chen, Hsin-Chu (TW); Shih-Hsien Yang, Hsin-Chu (TW); Yu-Chih Wang, Hsin-Chu (TW); and Kuo-Hsiang Chen, Hsin-Chu (TW)
Assigned to AU OPTRONICS CORPORATION, Hsin-Chu (TW)
Filed by AU Optronics Corporation, Hsin-Chu (TW)
Filed on May 17, 2022, as Appl. No. 17/746,477.
Claims priority of application No. 110143053 (TW), filed on Nov. 18, 2021.
Prior Publication US 2023/0154511 A1, May 18, 2023
Int. Cl. G11C 8/10 (2006.01); G11C 8/08 (2006.01); G11C 8/18 (2006.01)
CPC G11C 8/10 (2013.01) [G11C 8/08 (2013.01); G11C 8/18 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory chip, comprising:
a first encoding device configured to generate a plurality of word line signals; and
a memory device configured to generate a third data signal according to a first data signal and a second data signal, the memory device comprises:
a first memory circuit configured to generate the first data signal according to the plurality of word line signals at a first node during a first period; and
a second memory circuit configured to generate the second data signal according to the plurality of word line signals at a second node different from the first node during a second period after the first period.