US 11,996,161 B2
Apparatuses and methods including multilevel command and address signals
Kang-Yong Kim, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2022, as Appl. No. 17/805,270.
Application 17/805,270 is a division of application No. 16/875,798, filed on May 15, 2020, granted, now 11,386,940, issued on Jul. 12, 2022.
Claims priority of provisional application 62/854,525, filed on May 30, 2019.
Prior Publication US 2022/0301604 A1, Sep. 22, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an address decoder configured to receive address signals and provide decoded addresses;
a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations; and
a command/address input circuit configured to receive a plurality of multilevel command and address signals and provide output signals to the address decoder and the command decoder, wherein the output signals including signals representing binary values and signals representing non-binary values, wherein the signals representing binary values correspond to internal address signals and the signals representing non-binary values correspond to internal command signals.