US 11,996,156 B2
Semiconductor integrated circuit and memory system
Atsushi Tanaka, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 26, 2022, as Appl. No. 17/896,871.
Claims priority of application No. 2021-170289 (JP), filed on Oct. 18, 2021.
Prior Publication US 2023/0121722 A1, Apr. 20, 2023
Int. Cl. G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/12 (2013.01) [G11C 2029/1206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a write test circuit configured to generate test data and transmit the generated test data to an external memory device without storing the generated test data in a local memory device; and
a read test circuit configured to receive from the external memory device, read data that the external memory device has obtained by reading the generated test data, and compare the received read data with an expected value without storing either the received read data or the expected value in the local memory device, wherein
the write test circuit generates the test data according to a physical address of the local memory device, specified in a write command, and
the read test circuit is further configured to generate the expected value according to a physical address of the local memory device, specified in a read command.