	US 11,996,153 B2
	Three-dimensional memory device with separated contact regions and methods for forming the same
James Kai, Santa Clara, CA (US); Yuki Mizutani, San Jose, CA (US); Hisakazu Otoi, Yokkaichi (JP); Masaaki Higashitani, Cupertino, CA (US); and Hiroyuki Ogawa, Nagoya (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,298.
Application 17/556,298 is a continuation in part of application No. 17/397,678, filed on Aug. 9, 2021, granted, now 11,792,988.
Prior Publication US 2023/0044232 A1, Feb. 9, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); H01L 23/48 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)

CPC G11C 16/0483 (2013.01) [G11C 8/14 (2013.01); H01L 23/481 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)]

19 Claims

1. A semiconductor structure comprising a memory die, wherein the memory die comprises:

an alternating stack of insulating layers and electrically conductive layers overlying a substrate and laterally extending through a series of regions that comprises, in a spatial order along a first horizontal direction, a first contact region, a first memory array region, a second contact region, a second memory array region, a third contact region, and a third memory array region;

arrays of memory openings located in the first memory array region, the second memory array region, and the third memory array region; and

arrays of memory opening fill structures located within the arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements.