US 11,996,151 B2
Memory arrays and methods used in forming a memory array comprising strings of memory cells
Jordan D. Greenlee, Boise, ID (US); John D. Hopkins, Meridian, ID (US); Andrew Li, Boise, ID (US); and Alyssa N. Scarbrough, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 10, 2021, as Appl. No. 17/315,727.
Prior Publication US 2022/0359012 A1, Nov. 10, 2022
Int. Cl. H10B 41/27 (2023.01); G11C 16/04 (2006.01); H01L 29/161 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [H01L 29/161 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising:
a lowest of the first tiers comprising sacrificial material;
an uppermost tier; and
an intermediate tier vertically between the lowest first tier and the uppermost tier, the intermediate tier comprising at least one of silicon and germanium;
forming lower horizontally-elongated trenches through the uppermost tier and into the intermediate tier in the lower portion, the lower horizontally-elongated trenches individually being between immediately-laterally-adjacent of the memory-block regions;
reacting a metal halide with the at least one of the silicon and germanium to form sidewalls of the lower horizontally-elongated trenches in the intermediate tier to comprise the metal of the metal halide and that extends longitudinally-along the laterally-spaced memory-block regions in the intermediate tier;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion, and forming upper horizontally-elongated trenches in the upper portion that are individually directly above and extend longitudinally-along individual of the lower horizontally-elongated trenches; and
through the upper and lower horizontally-elongated trenches, replacing the sacrificial material in the lowest first tier with conductive material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier.