US 11,996,145 B2
Cross-point array with threshold switching selector memory element
Hans Jurgen Richter, Palo Alto, CA (US); and Michael K. Grobis, Campbell, CA (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 3, 2022, as Appl. No. 17/735,277.
Prior Publication US 2023/0360700 A1, Nov. 9, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/003 (2013.01) [G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/72 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a cross-point array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of memory cells, each memory cell connected between one of the first conductive lines and one of the second conductive lines, wherein each memory cell has a two-terminal threshold switching memory element having a non-conductive state in which the memory cell is unselected for access and a conductive state in which the memory cell is selected for access; and
one or more control circuits in communication with the cross-point array, the one or more control circuits configured to:
apply a first polarity programming signal to the two-terminal threshold switching memory element of a selected memory cell to cause the memory element to have a high-resistance state (HRS) in the conductive state when read by a read signal having the first polarity, wherein the HRS represents a first bit value; and
apply a second polarity programming signal to the two-terminal threshold switching memory element of the selected memory cell to cause the memory element to have a low-resistance state (LRS) in the conductive state when read by the read signal having the first polarity, wherein the LRS represents a second bit value, wherein the LRS has a lower resistance than the HRS.