US 11,996,144 B2
Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)
Jon D. Trantham, Chanhassen, MN (US); Praveen Viraraghavan, Chicago, IL (US); John W. Dykes, Eden Prairie, MN (US); Ian J. Gilbert, Chanhassen, MN (US); Sangita Shreedharan Kalarickal, Eden Prairie, MN (US); Matthew J. Totin, Excelsior, MN (US); Mohamad El-Batal, Superior, CO (US); and Darshana H. Mehta, Shakopee, MN (US)
Assigned to SEAGATE TECHNOLOGY LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Jun. 15, 2022, as Appl. No. 17/840,779.
Claims priority of provisional application 63/210,816, filed on Jun. 15, 2021.
Prior Publication US 2022/0399054 A1, Dec. 15, 2022
Int. Cl. G11C 11/56 (2006.01); G11C 11/22 (2006.01)
CPC G11C 11/5657 (2013.01) [G11C 11/221 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a non-volatile memory (NVM) comprising an array of semiconductor memory cells, each memory cell comprising first and second ferroelectric memory elements (FMEs), each of the first and second FMEs having at least one ferroelectric to store at least one bit in the memory cell; and
a control circuit configured to activate a common set of external control lines, coupled to a selected memory cell, in a selected order to read the at least one bit from the selected memory cell, wherein the selected order comprising applying a first set of control inputs to program the first FME and subsequently applying a second set of control inputs to program the second FME, the second FME requiring power level lower than the power level required by the first FME.