US 11,996,130 B2
Nonvolatile memory cell, nonvolatile memory cell array, and information writing method of nonvolatile memory cell array
Takashi Yokoyama, Kanagawa (JP); Mikio Oka, Kanagawa (JP); and Yasuo Kanda, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/627,839
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jun. 11, 2020, PCT No. PCT/JP2020/023048
§ 371(c)(1), (2) Date Jan. 18, 2022,
PCT Pub. No. WO2021/014810, PCT Pub. Date Jan. 28, 2021.
Claims priority of application No. 2019-135920 (JP), filed on Jul. 24, 2019.
Prior Publication US 2022/0262420 A1, Aug. 18, 2022
Int. Cl. G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A nonvolatile memory cell comprising:
a resistance-change nonvolatile memory element and a selection transistor, wherein
one end of the nonvolatile memory element is connected to one source/drain region of the selection transistor and is connected to a write line,
other source/drain region of the selection transistor is connected to a select line,
another end of the nonvolatile memory element is connected to a bit line,
the selection transistor and the write line are provided on a first surface side of a base portion made of a semiconductor material, and
the nonvolatile memory element is provided on a second surface side opposing the first surface of the base portion.