US 11,996,062 B2
Gate driving circuit and display panel
Yanqing Guan, Wuhan (CN); Chao Tian, Wuhan (CN); and Haiming Cao, Wuhan (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
Appl. No. 17/419,876
Filed by WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
PCT Filed May 31, 2021, PCT No. PCT/CN2021/097130
§ 371(c)(1), (2) Date Nov. 24, 2022,
PCT Pub. No. WO2022/241821, PCT Pub. Date Nov. 24, 2022.
Claims priority of application No. 202110539968.1 (CN), filed on May 18, 2021.
Prior Publication US 2023/0402019 A1, Dec. 14, 2023
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 2300/0876 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising a plurality of cascaded gate driving units, each of the driving units comprising:
a pull-up control module, electrically connected to a first node, configured to control a voltage level of the first node;
a pull-up module, electrically connected to the first node and a scan signal output end of a current stage, configured to pull up a voltage level of the scan signal output end of the gate driving unit of a current stage under a control of the voltage level of the first node;
a pull-down module, electrically connected to the scan signal output end of the gate driving unit of the gate driving unit of the current stage, configured to pull down the voltage level of the scan signal output end of the gate driving unit of the current stage; and
a pull-down control module, electrically connected to a second node, the first node, a first clock signal end and the scan signal output end of the gate driving unit of the current stage, configured to periodically pull down a voltage level of the second node under a control of an input signal of the first clock signal end to maintain the voltage level of the first node and the voltage level of the scan signal output end of the gate driving unit of the current stage.