US 11,996,051 B2
Display panel of an organic light emitting diode display device, and organic light emitting diode display device including pixels that differ in terms of sizes of at least one transistor and/or capacitor
Ji-Hyun Ka, Seongnam-si (KR); Nackhyeon Keum, Hwaseong-si (KR); and Kimyeong Eom, Suwon-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Feb. 6, 2023, as Appl. No. 18/106,431.
Application 18/106,431 is a continuation of application No. 17/199,851, filed on Mar. 12, 2021, granted, now 11,574,594.
Claims priority of application No. 10-2020-0097951 (KR), filed on Aug. 5, 2020.
Prior Publication US 2023/0186856 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01)
CPC G09G 3/3258 (2013.01) [G09G 3/3291 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0876 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel of a display device, the display panel comprising:
a first pixel configured to emit first color light;
a second pixel configured to emit second color light; and
a third pixel configured to emit third color light,
wherein each of the first, second and third pixels includes:
a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node;
a boost capacitor including a first electrode coupled to the gate node, and a second electrode coupled to a gate writing signal line;
a first transistor including a gate electrode coupled to the gate node;
a second transistor configured to transfer a data voltage to a source of the first transistor in response to a gate writing signal of the gate writing signal line;
a third transistor configured to diode-connect the first transistor in response to a gate compensation signal of a gate compensation signal line; and
a light emitting element including an anode, and a cathode coupled to a second power supply voltage line, and
wherein a ratio of a channel width to a channel length of the first transistor in the third pixel is greater than a ratio of a channel width to a channel length of the first transistor in the first pixel or the second pixel, and
wherein a size of the storage capacitor included in the third pixel is determined such that a data voltage range for the third pixel is adjusted close to a data voltage range for the first pixel or the second pixel.