CPC G06T 7/30 (2017.01) [G06F 18/22 (2023.01); G06T 5/50 (2013.01); G06T 7/001 (2013.01); H01J 37/261 (2013.01); G06T 2207/20221 (2013.01); G06T 2207/30148 (2013.01); H01J 2237/221 (2013.01)] | 19 Claims |
1. A computerized system of examination of a semiconductor specimen, the system comprising a processing and memory circuitry (PMC) configured to:
obtain a sequence of frames of an area of the semiconductor specimen, the sequence of frames being acquired by an electron beam tool configured to scan the area from a plurality of directions, the sequence of frames comprising a plurality of sets of frames wherein each set of frames is acquired from a respective direction; and
register the plurality of sets of frames and generate an image of the semiconductor specimen based on result of the registration, comprising:
in response to a determination of performing a first registration among the set of frames acquired from each direction, performing, for each direction, the first registration among the set of frames acquired therefrom and combining the registered set of frames to generate a first composite frame, thereby giving rise to a plurality of first composite frames respectively corresponding to the plurality of directions; and
performing a second registration among the plurality of first composite frames and combining the registered plurality of first composite frames to generate the image of the area of the semiconductor specimen, wherein the second registration is performed to correct offset between the plurality of first composite frames, the offset caused by directional scanning from the plurality of directions and related to scanning mechanism of the electron beam tool;
wherein the generated image of the semiconductor specimen possesses reduced image artifacts with respect to a frame scanned from a given direction of the plurality of directions, and wherein the image is usable for examination of the semiconductor specimen.
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