| CPC G06F 30/3953 (2020.01) [G03F 1/36 (2013.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01)] | 20 Claims |
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1. A method of fabricating a semiconductor device, comprising:
disposing a first standard cell on an area-oriented region and a second standard cell on a performance-oriented region, the performance-oriented region being spaced apart from the area-oriented region;
performing a routing operation on the first and second standard cells; and
fabricating the semiconductor device including the first and second standard cells,
wherein the performing of the routing operation comprises:
defining first routing tracks on the area-oriented region, a pitch between the first routing tracks being a first pitch;
defining second routing tracks on the performance-oriented region, a pitch between the second routing tracks being a second pitch greater than the first pitch;
disposing first routing patterns on the first routing tracks, respectively; and
disposing second routing patterns on the second routing tracks, respectively,
wherein a smallest line width of the first routing patterns is smaller than a smallest line width of the second routing patterns, and
wherein a smallest space of the first routing patterns is smaller than a smallest space of the second routing patterns.
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