	US 11,995,355 B2
	Memory system and shift register memory
Yuta Aiba, Yokohama (JP); Naomi Takeda, Yokohama (JP); and Masanobu Shirakawa, Chigasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Apr. 28, 2023, as Appl. No. 18/309,038.
Application 18/309,038 is a division of application No. 17/015,893, filed on Sep. 9, 2020, granted, now 11,675,535.
Claims priority of application No. 2020-050894 (JP), filed on Mar. 23, 2020.
Prior Publication US 2023/0305753 A1, Sep. 28, 2023
Int. Cl. G11C 19/08 (2006.01); G06F 3/06 (2006.01)

CPC G06F 3/0659 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0679 (2013.01); G11C 19/0841 (2013.01)]

11 Claims

1. A memory system comprising:

a shift register memory including a plurality of blocks each including a plurality of data storing shift strings, and configured to write and read data to and from each of the blocks using a last-in first-out method by shifting data stored in each of a plurality of layers included in each of the data storing shift strings in a first direction from an uppermost layer to a lowermost layer or in a second direction opposite to the first direction; and

a controller configured to control the shift register memory,

wherein the controller is configured to:

create likelihood information of first data read from each of a plurality of data storing shift strings in a first block, using hierarchical position information of each of the layers included in each of the data storing shift strings in the first block; and

perform soft decision decoding for the first data using the likelihood information.