US 11,995,352 B2
Memory controller and operating method thereof
Ki Young Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 17, 2022, as Appl. No. 17/746,304.
Claims priority of application No. 10-2021-0186786 (KR), filed on Dec. 24, 2021.
Prior Publication US 2023/0205458 A1, Jun. 29, 2023
Int. Cl. G06F 3/06 (2006.01); H04L 67/1097 (2022.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0607 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); H04L 67/1097 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a memory configured to store an activation candidate list including two or more nodes each indicating a logical address range that satisfies a preset activation candidate condition among a plurality of logical address ranges; and
a processor configured to:
determine a target node based on an activation parameter of logical address ranges indicated by respective nodes included in the activation candidate list,
determine, as activation logical address ranges, one or more logical address ranges from the activation candidate list based on the target node, and
transmit information indicating the activation logical address range to a host.