US 11,995,351 B2
DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine
Joseph L Greathouse, Santa Clara, CA (US); Sean Keely, Santa Clara, CA (US); Alan D. Smith, Santa Clara, CA (US); Anthony Asaro, Markham (CA); Ling-Ling Wang, Santa Clara, CA (US); Milind N Nemlekar, Santa Clara, CA (US); Hari Thangirala, Santa Clara, CA (US); and Felix Kuehling, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed on Nov. 1, 2021, as Appl. No. 17/515,976.
Prior Publication US 2023/0132931 A1, May 4, 2023
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A system, comprising:
a host processor communicably coupled to a parallel processor multi-chip module, wherein the parallel processor multi-chip module includes:
a base integrated circuit (IC) die including a plurality of processing stacked die chiplets 3D stacked on top of the base IC die, wherein the base IC die includes an inter-chip data fabric communicably coupling the processing stacked die chiplets together; and
a plurality of DMA engines 3D stacked on top of the base IC die, wherein the plurality of DMA engines are each configured to perform a portion of a data transfer requested by a DMA transfer command.