CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 13/28 (2013.01)] | 20 Claims |
16. A system, comprising:
a host processor communicably coupled to a parallel processor multi-chip module, wherein the parallel processor multi-chip module includes:
a base integrated circuit (IC) die including a plurality of processing stacked die chiplets 3D stacked on top of the base IC die, wherein the base IC die includes an inter-chip data fabric communicably coupling the processing stacked die chiplets together; and
a plurality of DMA engines 3D stacked on top of the base IC die, wherein the plurality of DMA engines are each configured to perform a portion of a data transfer requested by a DMA transfer command.
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