US 11,995,345 B2
Plane balancing in a memory system
John J Kane, Westminster, CO (US); Byron D Harris, Mead, CO (US); and Vivek Shivhare, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 13, 2022, as Appl. No. 17/864,192.
Claims priority of provisional application 63/348,298, filed on Jun. 2, 2022.
Prior Publication US 2023/0393779 A1, Dec. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A method, comprising:
selecting a memory die for a parallel write operation for writing a set of data, the memory die comprising a plurality of planes each comprising a respective plurality of blocks of memory cells;
determining, based at least in part on the memory die being selected for the parallel write operation, a plane of the plurality of planes that has a lowest quantity of blocks available for writing relative to the other planes in the plurality of planes; and
excluding at least the plane from the parallel write operation based at least in part on the plane having the lowest quantity of blocks available for writing and based at least in part on determining that a difference between the lowest quantity of blocks and a reference quantity satisfies a threshold.