US 11,995,334 B2
Memory system including a memory controller
Jae-Han Park, Gyeonggi-do (KR); and Hyun-Woo Kwack, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 6, 2022, as Appl. No. 17/903,139.
Application 17/903,139 is a division of application No. 16/591,974, filed on Oct. 3, 2019, granted, now 11,474,727.
Application 16/591,974 is a continuation of application No. 15/944,436, filed on Apr. 3, 2018, granted, now 10,725,688, issued on Jul. 28, 2020.
Application 15/944,436 is a continuation of application No. 15/808,367, filed on Nov. 9, 2017, granted, now 9,965,214, issued on May 8, 2018.
Application 15/808,367 is a continuation of application No. 15/423,012, filed on Feb. 2, 2017, granted, now 9,841,922, issued on Dec. 12, 2017.
Claims priority of provisional application 62/290,697, filed on Feb. 3, 2016.
Prior Publication US 2022/0413736 A1, Dec. 29, 2022
Int. Cl. G11C 5/04 (2006.01); G06F 3/06 (2006.01); G11C 11/00 (2006.01); G11C 7/10 (2006.01)
CPC G06F 3/0647 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G11C 5/04 (2013.01); G11C 11/00 (2013.01); G11C 7/10 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory module comprising:
a first memory chip group configured to transfer a first data to a memory controller through a first signal line group;
a second memory chip group configured to transfer a second data to the memory controller through a second signal line group; and
a registering clock driver configured to transfer a clock signal to the first memory chip group or the second memory chip group,
wherein signal lines of the first signal line group and signal lines of the second signal line group are disposed along same row direction, and
wherein the registering clock driver provides the clock signal to at least one of the first memory chip group and the second memory chip groups based on an enabling signal.