| CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 33 Claims |
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1. A memory controller for controlling a memory device storing plural pieces of data and plural write sequence indexes and plural pieces of barrier information corresponding to the plural pieces of data, the memory controller comprising:
a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”;
a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and
a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.
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