a processor;

a first storage device supporting a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol, the first storage device including a first address range;

a second storage device supporting the cache coherent interconnect protocol, the second storage device including a second address range, the second storage device providing a redundant array of independent disks (RAID) address range associated with the first address range and the second address range; and

a decoder associated with the second storage device, the decoder configured to receive a request from the processor, the request using the byte level protocol and including a byte address in the RAID address range, and to determine that the byte address in the RAID address range is associated with a target address range,

wherein the first storage device and the second storage device are included in a RAID.