US 11,995,270 B2
Sensor control board, display apparatus, and control method for display apparatus
Yoshihiro Kotani, Saitama (JP); and Kei Dobashi, Saitama (JP)
Assigned to Wacom Co., Ltd., Saitama (JP)
Filed by Wacom Co., Ltd., Saitama (JP)
Filed on Mar. 24, 2023, as Appl. No. 18/190,021.
Claims priority of application No. 2022-052588 (JP), filed on Mar. 28, 2022.
Prior Publication US 2023/0305660 A1, Sep. 28, 2023
Int. Cl. G06F 3/041 (2006.01); G06F 3/038 (2013.01); G09G 3/36 (2006.01)
CPC G06F 3/04184 (2019.05) [G06F 3/0383 (2013.01); G06F 3/0412 (2013.01); G06F 3/04162 (2019.05); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0247 (2013.01); G09G 2354/00 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A sensor control board in a display apparatus that includes a display device and a position detector, the display device including a plurality of image elements each having a first one end that receives input of a common potential and a second end that receives input of an individual potential, the image elements being arrayed in a grid pattern, the position detector located either above or below the display device, the position detector detecting a pointed position on the display device, the sensor control board outputting a transmission signal to the position detector, the sensor control board comprising:
a clock generation circuit which, in operation, generates a clock signal;
a phase adjustment circuit which, in operation, adjusts a phase of the clock signal such that the phase is inverted at each predetermined timing and output an adjusted clock signal as the transmission signal to the position detector; and
an output circuit which, in operation, outputs the clock signal generated by the clock generation circuit to the phase adjustment circuit or stops outputting the clock signal to the phase adjustment circuit,
wherein the clock generation circuit is connected to the phase adjustment circuit via the output circuit,
wherein over a plurality of third periods each made up of a first period and a plurality of second periods subsequent to and shorter than the first period, the output circuit outputs the clock signal during the first and the second periods, and
wherein the predetermined timing is a timing at which each of the third periods is started.