| CPC G06F 21/76 (2013.01) [G06F 21/755 (2017.08)] | 6 Claims |
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1. A security apparatus for use in a logic circuit having at least one encodable logic input and at least one un-encoded output, comprising:
a secure section and an unsecure section, wherein said secure section is inaccessible to malicious intrusion through secure fabrication, so as to secure said logic circuit;
wherein said secure section further comprises:
at least two logic inputs connected to an external data source that does not impede upon the said secure section;
a random logic state generator for randomly outputting a secure random logic state 1 or 0;
a first logic gate utilizing said secure random logic state to encode said at least one encodable logic input by implementing said encoding via a randomized dual-rail encoding so as to produce a pair of securely encoded logic outputs;
wherein said pair of securely encoded logic outputs, following processing by an arbitrary logic function, that does not operate on a output of a single logic gate, are connected to at least one pair of securely decodable logic outputs of unsecure section for input into an area of the secure section for secure decoding of the said at least one pair of securely decodable logic outputs to produce an external output;
a multiplexer for selecting one of at least one pair of securely decodable logic inputs from said external area of said unsecure section; and
a second logic gate utilizing said secure random logic state to un-encode said selected securely decodable logic input so as to produce an un-encoded logic output from said logic circuit.
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