US 11,995,218 B2
Processor with a configurable distribution of privileged resources and exceptions between protection rings
Pierre Guironnet De Massas, Allevard (FR); Vincent Ray, Allevard (FR); and Benoit Dupont De Dinechin, Grenoble (FR)
Assigned to Kalray, Montbonnot Saint Martin (FR)
Filed by Kalray, Montbonnot Saint Martin (FR)
Filed on Dec. 31, 2020, as Appl. No. 17/139,662.
Claims priority of application No. 1915755 (FR), filed on Dec. 31, 2019.
Prior Publication US 2021/0200904 A1, Jul. 1, 2021
Int. Cl. G06F 21/71 (2013.01); G06F 21/74 (2013.01)
CPC G06F 21/71 (2013.01) [G06F 21/74 (2013.01); G06F 2221/2113 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A processor comprising:
multiple protection rings of increasing privilege levels assigned to respective software layers including a combination selected from an application program, an operating system, a virtual machine hypervisor, and a debugger;
a processor status register storing a protection ring in which a current instruction of a software layer is executed;
multiple privileged hardware resources including at least (i) execution units responsive to specific instructions and (ii) configuration registers;
a programmable resource ownership table implemented in the configuration registers, assigning each privileged resource to a respective protection ring; and
wherein the processor is configured to compare the current protection ring stored in the status register with a ring programmed in the ownership table for a privileged resource accessed by the current instruction, and trigger a privilege trap when the comparison fails.