US 11,995,184 B2
Low-latency digital signature processing with side-channel security
Santosh Ghosh, Hillsboro, OR (US); Andrea Basso, London (GB); and Manoj Sastry, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,870.
Prior Publication US 2022/0012334 A1, Jan. 13, 2022
Int. Cl. G06F 21/55 (2013.01); G06F 7/72 (2006.01); G06F 21/64 (2013.01); G06F 21/75 (2013.01); H04L 9/00 (2022.01); H04L 9/30 (2006.01); H04L 9/32 (2006.01)
CPC G06F 21/556 (2013.01) [G06F 7/724 (2013.01); G06F 21/64 (2013.01); G06F 21/75 (2013.01); H04L 9/003 (2013.01); H04L 9/3093 (2013.01); H04L 9/3247 (2013.01); G06F 2207/7223 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and
one or more accessory operation circuits coupled with the NTT/INTT coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit;
wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory, and wherein the computation by the one or more accessory operation circuits is performed without retrieving the results of the operations of the NTT/INTT coefficient multiplier circuit from the memory.