CPC G06F 21/554 (2013.01) [G06F 2221/034 (2013.01)] | 24 Claims |
1. A computing apparatus comprising:
a processor circuit at an intrusion detection system of an autonomous system having a first control system and a second control system; and
memory storing instructions, which when executed by the processor circuit causes the processor circuit to:
receive a context associated with the autonomous system;
receive a contract based on the context, the contract comprising an indication of acceptable actions for the autonomous system when the first control system is disconnected from the autonomous system;
detect an attack on the autonomous system;
generate, responsive to the attack, at least one command according to the contract; and
send the command to the second control system of the autonomous system.
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