US 11,995,017 B2
Multi-plane, multi-protocol memory switch fabric with configurable transport
Thomas Norrie, Mountain View, CA (US); Shrijeet Mukherjee, Mountain View, CA (US); John Greth, Mountain View, CA (US); Rochan Sankar, Mountain View, CA (US); Shimon Muller, Mountain View, CA (US); Ariel Hendel, Mountain View, CA (US); and Gurjeet Singh, Mountain View, CA (US)
Assigned to Enfabrica Corporation, Mountain View, CA (US)
Filed by Enfabrica Corporation, Mountain View, CA (US)
Filed on Jun. 8, 2022, as Appl. No. 17/835,472.
Claims priority of provisional application 63/208,618, filed on Jun. 9, 2021.
Prior Publication US 2022/0398207 A1, Dec. 15, 2022
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 2213/0026 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A multi-plane, multi-protocol memory switch comprising:
a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints;
a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint, wherein the cacheline exchange engine is configured to:
receive a data payload from a source device;
write the data payload in a first address space of the source device;
map the first address space into a second address space of a destination device, wherein mapping is performed through internal endpoint memory space; and
write the data payload in the second address space of the destination device; and
a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address, wherein facilitating the data-exchange includes bulk data transfer based on a comparison between a forwarding packet header generated based on the source and destination addresses for the data stream and a range of forwarding addresses reserved for the memory switch.