a data bus;

a clock bus;

a control bus;

an application processor connected to the data bus and the clock bus;

a plurality of image sensors connected together in a daisy chain using the control bus, the image sensors configured to selectively connect to the data bus and the clock bus and a first image sensor among the image sensors is configured as a master,

wherein the master outputs first image data to the data bus, outputs a first clock signal to the clock bus, and sends a first control signal to a second image sensor among the image sensors in the daisy chain through the control bus,

wherein the first control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends, wherein the second image sensor connects itself to the data bus and the clock bus upon determining that the first control signal has the second logic state, and wherein the master disconnects itself from the data bus and the clock bus a period of time after setting the first control signal to the second logic state.