US 11,995,001 B2
Supporting secure memory intent
Krystof C. Zmudzinski, Forest Grove, OR (US); Siddhartha Chhabra, Portland, OR (US); Uday R. Savagaonkar, Portland, OR (US); Simon P. Johnson, Beaverton, OR (US); Rebekah M. Leslie-Hurd, Portland, OR (US); Francis X. McKeen, Portland, OR (US); Gilbert Neiger, Portland, OR (US); Raghunandan Makaram, Northborough, MA (US); Carlos V. Rozas, Portland, OR (US); Amy L. Santoni, Scottsdale, AZ (US); Vincent R. Scarlata, Beaverton, OR (US); Vedvyas Shanbhogue, Austin, TX (US); Ilya Alexandrovich, Yokneam Illit (IL); Ittai Anati, Ramat Hasharon (IL); Wesley H. Smith, Raleigh, NC (US); and Michael Goldsmith, Lake Oswego, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 18, 2022, as Appl. No. 17/867,306.
Application 17/867,306 is a continuation of application No. 17/156,175, filed on Jan. 22, 2021, granted, now 11,392,507.
Application 17/156,175 is a continuation of application No. 16/402,442, filed on May 3, 2019, granted, now 10,922,241, issued on Feb. 16, 2021.
Application 16/402,442 is a continuation of application No. 15/861,364, filed on Jan. 3, 2018, granted, now 10,282,306, issued on May 7, 2019.
Application 15/861,364 is a continuation of application No. 14/738,037, filed on Jun. 12, 2015, granted, now 9,875,189, issued on Jan. 23, 2018.
Prior Publication US 2023/0042288 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/1027 (2016.01); G06F 12/1036 (2016.01); G06F 12/1045 (2016.01); G06F 12/109 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 9/455 (2013.01); G06F 9/45558 (2013.01); G06F 12/1027 (2013.01); G06F 12/1036 (2013.01); G06F 12/109 (2013.01); G06F 12/1441 (2013.01); G06F 2009/45583 (2013.01); G06F 12/1045 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/151 (2013.01); G06F 2212/657 (2013.01); G06F 2212/684 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor including:
a shared cache; and
a plurality of cores, including a first core, coupled to the shared cache, the first core including:
a decode unit to decode instructions, including a given instruction indicating a given virtual address;
at least one translation lookaside buffer (TLB) to store translations of virtual addresses to physical addresses;
a page miss handler to perform a page table walk in page tables to identify a page table entry to map the given virtual address to a corresponding physical address of a memory and having a security indicator bit corresponding to the physical address, the security indicator bit to either have a first value to indicate a page of the memory at the physical address is an encrypted page, or have a different value than the first value to indicate the page of the memory is an unencrypted page;
a plurality of memory controllers, including a first memory controller, coupled with the interconnect, the first memory controller to control access to the page of the memory;
a memory encryption engine to encrypt data stored to the page of a memory, and decrypt data read from the page of a memory, if the security indicator bit is set to one;
a register to indicate which bit of the page table entry is the security indicator bit, wherein the register is readable by software;
a plurality of bus controller units coupled with the interconnect, the plurality of bus controller units to control access to a bus; and
a system agent unit coupled with the interconnect, the system agent unit to regulate a power state of the plurality of cores.