US 11,995,000 B2
Packet cache system and method
Jiazhen Zheng, Santa Clara, CA (US); Srinivas Vaduvatha, San Jose, CA (US); Hugh McEvoy Walsh, Los Gatos, CA (US); Prashant R. Chandra, San Jose, CA (US); Abhishek Agarwal, Santa Clara, CA (US); Weihuang Wang, Los Gatos, CA (US); and Weiwei Jiang, Santa Clara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,018.
Prior Publication US 2023/0393987 A1, Dec. 7, 2023
Int. Cl. G06F 12/0895 (2016.01); G06F 12/0864 (2016.01); G06F 12/121 (2016.01)
CPC G06F 12/0895 (2013.01) [G06F 12/0864 (2013.01); G06F 12/121 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A packet cache system comprising:
a memory allocator for assigning a memory address to a packet;
a cache memory allocator for receiving the memory address corresponding to a non-cache memory and allocated to the packet, and associating the memory address with a cache memory address;
a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value;
a cache memory for storing the packet at a location indicated by the cache memory address; and
an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high,
wherein the memory allocator is operable to form the packet into one or more cells, the one or more cells comprising a control cell when the packet is formed into one cell, and comprising a control cell and one or more data cells when the packet is formed into more than one cell, wherein the memory allocator assigns the memory address to the control cell, and respectively assigns one or more additional memory addresses to the one or more data cells.