US 11,994,997 B2
Memory controller to manage quality of service enforcement and migration between local and pooled memory
Francesc Guim Bernat, Barcelona (ES); Karthik Kumar, Chandler, AZ (US); and Mark A. Schmisseur, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,431.
Prior Publication US 2021/0117334 A1, Apr. 22, 2021
Int. Cl. G11C 16/04 (2006.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 12/0831 (2016.01); G06F 12/0882 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0882 (2013.01) [G06F 9/5016 (2013.01); G06F 12/0238 (2013.01); G06F 12/0835 (2013.01); G06F 13/1668 (2013.01); G06F 2209/5011 (2013.01); G06F 2209/504 (2013.01); G06F 2209/508 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
one or more substrates; and
a logic coupled to the one or more substrates, where the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to:
communicate with a local memory and with a pooled memory controller to track memory page usage on a per application basis for a plurality of applications,
instruct the pooled memory controller to perform a quality of service enforcement in response to a determination that an application is latency bound or bandwidth bound, wherein the determination that the application is latency bound or bandwidth bound is based on a cycles per instruction determination, and
instruct a Direct Memory Access engine to perform a migration from a remote memory to the local memory in response to a determination that a quality of service cannot be enforced.