a memory array including memory cells to store memory data;

a memory controller operatively coupled to the memory array and including:

a prefetch buffer;

a read address buffer including an M memory register buffer to store addresses of memory read requests received from multiple separate devices and preserve N memory registers of the M memory registers, wherein M and are positive integers and N is less than M; and

logic circuitry configured to:

store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer;

omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer;

shift read addresses stored in M-N registers of the M memory registers when the address of the read request is continuous to a read address of the one of the M-N registers and not continuous to a read address of the N registers and preserving the read addresses stored in the N registers; and

flushing a register of the N registers when the address of the current read request is continuous to a read address stored in the register of the N registers.