US 11,994,991 B1
Cache memory device and method for implementing cache scheduling using same
Do Hun Kim, Yongin-si (KR); Keebum Shin, Seongnam-si (KR); and Kwangsun Lee, Yongin-si (KR)
Assigned to MetisX CO., Ltd., Yongin-si (KR)
Filed by MetisX CO., Ltd., Yongin-si (KR)
Filed on Nov. 14, 2023, as Appl. No. 18/508,840.
Claims priority of application No. 10-2023-0051365 (KR), filed on Apr. 19, 2023.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0817 (2016.01); G06F 12/0877 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 12/0877 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A cache memory device comprising:
a request reception unit configured to receive input transactions;
a traffic monitoring module configured to monitor traffic of the input transactions;
N cache schedulers, wherein N is an integer greater than or equal to 2;
a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and
an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers,
wherein setting the N input transaction regions by the region setting module comprises:
generating a histogram representing the number of memory accesses to addresses of the input transactions;
computing locations in the histogram where integral values for each of the N input transaction regions are equal; and
setting the N input transaction regions based on the computed locations, and
wherein the setting the N input transaction regions by the region setting module is performed if there are no input transactions remaining in all or at least some of the N cache schedulers.